The present invention relates to a memory cell for data storage applications, and more particularly, to embodiments of a memory cell including a magnetic tunnel junction (MTJ) memory element coupled to a selector device that exhibits asymmetric conductance.
Spin transfer torque magnetic random access memory (STT-MRAM) is a new class of non-volatile memory, which can retain the stored information when powered off. An STT-MRAM device normally comprises an array of memory cells, each of which may include a magnetic memory element and a selection element coupled in series between appropriate electrodes. The selector element may be a three terminal device, such as transistor, or a two-terminal device, such as diode or Ovonic threshold switch (OTS). Upon application of a switching current through the magnetic memory element, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a memory array 30, which comprises a plurality of memory cells 32 with each of the memory cells 32 including a two-terminal selector 34 coupled to a magnetic memory element 36 in series; a first plurality of parallel wiring lines 38A-C with each being coupled to a respective row of the magnetic memory elements 36 in a first direction; and a second plurality of parallel wiring lines 40A-C with each being coupled to a respective row of the selectors 34 in a second direction substantially perpendicular to the first direction. Accordingly, the memory cells 32 are located at the cross points between the first and second plurality of wiring lines 38A-C and 40A-C. The first and second plurality of wiring lines 38A-C and 40A-C may be word lines and bit lines, respectively, or vice versa. Multiple layers of the memory array 30 may be stacked to form a monolithic three-dimensional memory device.
FIG. 2 illustrates a scheme for programming a memory cell 32BB in the memory array 30 of FIG. 1. The memory cell 32BB to be programmed is selected by applying a programming voltage, V, to one of the second wiring lines 40B coupled thereto, while grounding one of the first wiring lines 38B connected to the memory cell 32BB, thereby generating a potential difference of V across the memory cell 32BB for programming. Meanwhile, to minimize current leakage and prevent accidental programming of the unselected memory cells, a voltage of about V/2 is applied to the unselected second wiring lines 40A, 40C-D, and the unselected first wiring lines 38A, 38C, resulting in a potential difference of V/2 across the unselected memory cells 32BA, 32AB, 32CB, 32DB, 32BC that are coupled to either the selected first wiring line 38B or the selected second wiring line 40B. The voltage value V/2 is less than the threshold voltage, Vth, for the selector to become conductive, thereby preventing unintended programming of the unselected memory cells 32BA, 32BC connected to the selected second wiring line 40B. The rest of the unselected memory cells 32AA, 32CA, 32DA, 32AC, 32CC, and 32DC that are not connected to the selected first wiring line 38B or the selected second wiring line 40B experience essentially no potential drop thereacross, thereby minimizing current leakage.
Referring back to FIG. 1, the magnetic memory element 36 normally includes a magnetic reference layer and a magnetic free layer with an electron tunnel junction layer interposed therebetween. The magnetic reference layer, the electron tunnel junction layer, and the magnetic free layer collectively form a magnetic tunnel junction (MTJ). Upon the application of an appropriate current through the MTJ, the magnetization direction of the magnetic free layer can be switched between two directions: parallel and anti-parallel with respect to the magnetization direction of the magnetic reference layer. The electron tunnel junction layer is normally made of an insulating material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions of the magnetic free and reference layers are substantially parallel or oriented in a same direction, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistance of the MTJ. Conversely, the electrical resistance of the MTJ is high when the magnetization directions of the magnetic reference and free layers are substantially anti-parallel or oriented in opposite directions. The stored logic in the magnetic memory element can be switched by changing the magnetization direction of the magnetic free layer between parallel and anti-parallel with respect to the magnetization direction of the reference layer. Therefore, the MTJ has two stable resistance states that allow the MTJ to serve as a non-volatile memory element.
Based on the relative orientation between the magnetic reference and free layers and the magnetization directions thereof, an MTJ can be classified into one of two types: in-plane MTJ, the magnetization directions of which lie substantially within planes parallel to the same layers, or perpendicular MTJ, the magnetization directions of which are substantially perpendicular to the layer planes.
FIGS. 3A and 3B illustrate the programming operations of an STT-MRAM cell including a perpendicular MTJ memory element 80 coupled to a two-terminal selector 82 in series. The MTJ memory element 80 includes a magnetic reference layer 84 having an invariable or fixed magnetization direction 86 perpendicular to the layer plane thereof, a magnetic free layer 88 having a variable magnetization direction 90 or 96 perpendicular to the layer plane thereof, and a tunnel junction layer 92 interposed therebetween.
FIG. 3A illustrates the writing or programming process for switching the resistance state of the MTJ memory element 80 from high to low. As electrons that pass through the magnetic reference layer 84 are being spin-polarized, the spin-polarized electrons exert a spin transfer torque on the magnetic free layer 88. When the spin-polarized current or parallelizing current (ip) 98 exceeds a threshold level, the magnetic free layer 88 switches from the anti-parallel to parallel magnetization direction 90 with respect to the fixed magnetization direction 86 of the magnetic reference layer 84. It should be noted that the parallelizing write current (ip) 98 flows in the opposite direction as the electrons.
Conversely, FIG. 3B illustrates the writing process for switching the resistance state of the MTJ memory element 80 from low to high. As electrons pass through the magnetic free layer 88, the electrons with the same spin direction as that of the magnetization in the magnetic reference layer 84 pass into the magnetic reference layer 84 unimpeded. However, the electrons with the opposite spin direction are reflected back to the magnetic free layer 88 at the boundary between the tunnel junction layer 92 and the magnetic reference layer 84, causing the magnetization direction 96 of the magnetic free layer 88 to switch from the parallel to anti-parallel orientation when the anti-parallelizing current (iap) 100 exceeds a threshold level.
FIG. 4 shows an exemplary current-voltage (I-V) response plot for a bi-directional two-terminal selector. The I-V response curve 110 shows the magnitude of electric current passing through the two-terminal selector element as the voltage applied thereto varies. Initially, the current slightly increases with the applied voltage from zero to near a threshold voltage, Vth. At or near Vth, the current rapidly increases and exhibits a highly non-linear exponential behavior, indicating a transition of the selector from a nominally insulative or “off” state to a nominally conductive or “on” state. As the selector voltage continues to increase beyond Vth, the current increase becomes gradual until reaching VP, which may be the programming voltage required to drive a switching current through a magnetic memory element coupled to the selector. The current response behaves like a step function as the applied voltage increases from zero to VP with the sharp increase occurring at or near Vth, which may be about 60-80% of VP. As previously shown in FIG. 2, during the programming operation, the unselected memory cells coupled to either the selected word line or the selected bit line are subjected to a net applied voltage equivalent to about half the programming voltage. Therefore, the leakage current, Ileak, for the selector in the “off” state is measured at the selector voltage of VP/2. The ratio of Ion, which is the selector current at VP, to Ileak measured at VP/2 is sometimes referred to as “on/off ratio.”
With continuing reference to FIG. 4, as the selector voltage decreases from VP to near a holding voltage, Vhold, which is lower than Vth, the selector current gradually decreases and the selector remains in the highly conductive state. At or near Vhold, the current rapidly decreases and exhibits a highly non-linear behavior, indicating a transition from the nominally conductive state back to the nominally insulative state. As the voltage continues to decrease beyond Vhold, the current flow slightly decreases until stopping at about 0 V.
The I-V response curve 110 of the selector behaves like a hysteresis loop. The nominally insulating selector turns on or becomes conductive when the selector voltage exceeds Vth. Once in the conductive state, the selector will stay on or remain conductive until the selector voltage dropping below Vhold, which is less than Vth. In a conventional write or programming operation, the selector is first turned on by raising the selector voltage to about Vth. The selector voltage is then further increased to a higher level VP that is sufficient to drive a current Ion for switching the resistance state of the magnetic memory element. In a conventional read or sensing operation, the selector is first turned on by raising the selector voltage to about Vth. The selector voltage is then decreased to a level between Vth and Vhold to minimize “read disturbance” while ensuring that the selector is sufficiently conductive to allow a sensing current to pass therethrough for determining the resistance state of the magnetic memory element.
The two-terminal selector characterized by the I-V response plot of FIG. 4 is bi-directional as the polarity of the selector voltage may be reversed from zero to V′P as shown. The I-V response curve 110′ corresponding to the opposite polarity may be substantially similar to the curve 110 described above. The two response curves 110 and 110′ for the selector are therefore substantially “symmetric” with respect to the current (vertical) axis at Selector Voltage=0.
A bi-directional selector may alternatively have an I-V response shown in FIG. 5. The I-V response plot of FIG. 5 differs from the I-V response plot of FIG. 4 in that after the selector is turned on at Vth, the current remains substantially constant with continuously increasing selector voltage or decreasing selector voltage until reaching Vhold, below which the selector is turned off. The constant current is sometimes referred to as “compliance current” (Icc).